In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.

We have analyzed a displayed image of TFT-LCD three-dimensionally in case of low power drive using Multi-Field Driving Method (MFD). We have also proposed a concept of multi-media driving method using MFD in which a displayed image was divided into some interlaced subfield images and the number of interlaced subfields can be changed depending on the moving quantities of displayed images. This method made it possible not only to reduce a driving power consumption in case of still images to less than half, compared to that with conventional methods, but also to maintain high moving image quality.

In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.

In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.

This paper proposes a new method for dynamically controlling the clock speed of a processor in order to reduce power consumption without decreasing system performance. It automatically tunes the processor's speed by monitoring its activities and avoiding useless work so as not to exhaust the battery energy. Experiments with performance bottlenecks caused by disk activities show that the proposed method is very effective in comparison with the traditional one, in which the processor's speed is fixed.

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.

We have developed a new type of phase interpolation DDS with a digitally controlled delay generator. The new DDS is similar to a sine output DDS in that it produces low spurious signals, but it does not require a sine look-up table. Periodic jitter in the MSB of the DDS accumulator is reduced with the digitally controlled delay generator. Experimental results confirm successful frequency synthesizer operation in which the spurious signal level is successfully reduced to less than that the MSB of the accumulator.

We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.

We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.

Media processors have emerged so that a single LSI can realize multiple multimedia functions, such as graphics, video, audio and telecommunication with effectively shared hardware and flexible software. First, the difference between media processors and general-purpose microprocessors with multimedia extensions is clarified. Features for processes and data in the multimedia applications are summarized and are followed by the multimedia enhancements that the recent general-purpose microprocessors use. The architecture for media processors reflects the further optimized utilization of these features and realizes better price-performance ratio than the general-purpose microprocessors. Finally, the future directions of media processors are estimated, based on the performance, the power dissipation and the die size of the present microprocessors with multimedia extensions and the present media processors. The demand to improve the price-performance ratio for the whole system and to reduce the power consumption makes the media processor evolve into a system processor, which integrates not only the media processor but also the function of a general-purpose microprocessor, various interfaces and DRAMs.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.

This paper discusses a power save management method appropriate for the features of the fiber-optic access network based on Passive Double Star (PDS) topology, where PDS termination processing LSIs for the Optical Network Unit (ONU) operate intermittently and the usage rate is low at the residential customer. We developed PDS termination processing LSIs for the ONU, performed power management, and evaluated the degree of consumed power.

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of a 10 µA quiescent current opamp.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.